Area and Performance Optimization of Barrier Synchronization on Multi-core Network-on-Chips

Barrier synchronization is commonly and widely used to synchronize the execution of parallel processor cores on multi-core Network-on-Chips (NoCs). Since its global nature may cause heavy serialization resulting in large performance penalty, barrier synchronization should be carefully designed to have low latency communication and to minimize overall completion time. Therefore, in the paper, we propose a fast barrier synchronization mechanism, targeting Multi-core NoCs. The fast barrier synchronization mechanism includes a dedicated hardware module, named Fast Barrier Synchronizer (FBS), integrated with each processor node. It offers a set of barrier counters and can concurrently process synchronization requests issued by the local node and remote nodes via the on-chip network. The salient feature of our fast barrier synchronization mechanism is that, once the barrier condition is reached, the “barrier release” acknowledgement is routed to all processor nodes in a broadcast way in order to save chip area by avoiding storing source node information and to minimize completion time by avoiding serialization of barrier releasing. Synthesis results suggest that the FBS can run over 1 GHz in SMIC 130nm technology with small area overhead. We implemented a FBS-enhanced multi-core NoC architecture on our FPGA platform using the Xilinx Virtex 5 as the FPGA chip. FPGA utilization and simulation results show that our fast barrier synchronization demonstrates both area and performance advantages over the barrier synchronization counterpart with unicast barrier releasing. Keywords-Barrier Synchronization; Multi-core; Network-on-